1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device for reading stored data at an increased speed without causing a delay in the speed for writing data.
2. Description of the Related Art
As disclosed in Japanese laid-open patent publications Nos. 4-278297, 6-302190, and 8-46159, nonvolatile semiconductor memory devices are generally also called EEPROM (Electrically Erasable Programmable ROM). One known EEPROM that can be fabricated as a highly integrated circuit is a NAND-cell-type EEPROM comprising a plurality of series-connected memory transistors. Each of the memory transistors has a MOSFET structure including a floating gate and a control gate that are accumulated on a semiconductor substrate with an insulating film interposed therebetween. The memory transistors are connected in series such that adjacent ones of the memory transistors share a source and a drain. The NAND cells are arranged in a matrix, making up a memory cell array. Drains at ends of the NAND cells arranged along the columns of the memory cell array are connected in common to a bit line through respective selection gate transistors, and sources at opposite ends of the NAND cells are connected to a common source line through respective selection gate transistors. Control gates of the memory transistors and gate electrodes of the selection gate transistors are connected in common to a control gate line (word line) and a selecting gate line, respectively, along the rows of the memory cell array.
Data are written successively from memory transistors that are farther from the bit line. In the case of an n channel, a high potential (20 V or the like) is applied to the control gate of a selected memory transistor, and an intermediate potential (e.g., 10 V) is applied to the control gate of an unselected memory transistor positioned closer to the bit line than the selected memory transistor and the gate of a selection gate transistor. At this time, the potential of the bit line is transmitted via the selection gate transistor and the unselected memory transistor to the drain of the selected memory transistor.
For writing data "1", a high electric field is applied between the gate and drain of the selected memory transistor, and electrons are injected from the substrate into the floating gate, changing the threshold of the selected memory transistor in a positive direction. When data to be written is "0" or is not present, there are no threshold changes.
For erasing data, a high potential is applied to the p-type substrate, and a potential of 0 V is applied to the control gates of all the memory transistors and the gates of the selection gate transistors. In all the memory transistors, electrons of the floating gates are discharged into the substrate, changing the threshold in a negative direction.
For reading data, a selection gate transistor and an unselected memory transistor which is closer to the bit line than the selected memory transistor are turned on, and a potential of 0 V is applied to the gate of the selected memory transistor. At this time, data "0" or "1" is determined by reading a current flowing through the bit line.
In the conventional nonvolatile semiconductor memory devices, since a high potential is supplied to the bit line for writing data, the selected transistors need to comprise transistors having a high withstand voltage (large resistance). Therefore, when data are read, the current drive capability is lowered, and the speed at which to read the data is reduced. If enhanced transistors having a large current drive capability are used as the selected transistors for achieving a desired data reading speed, then it is necessary to lower the writing drain potential as no withstand voltage is available when writing data, resulting in a reduction in the data writing speed. These problems are caused because one selected transistor is used for both writing data and reading data.